FPGA based bandwidth adjustable all digital direct frequency synthesizer

A design is presented for a bandwidth adjustable all digital DDFS. The DDFS architecture is based on a lookup table implemented through a compressed ROM. A single-bit DAC that uses pulse width modulation (PWM) technique has been employed in the last stage for producing analog output signal. A programmable lowpass RC filter has been designed that is controlled by the bandwidth control word. Complete system has been implemented on a xilinx Spartan FPGA. The digital clock manager of FPGA device has been employed to generate multiples of the system clock to compensate bandwidth reduction effect of the single-bit DAC as well as to manage the power budget. ROM compression has been achieved by separately generating the two most significant amplitude bits by a combinational circuit. This arrangement provides an additional 20% compression of ROM. An SFDR of about 66 dBc has been achieved for pre DAC stage.