The Effect of Temperature on Lateral DMOS Transistors in a Power IC Technology

A systematic study of the effects of elevated temperature on the lateral DMOS power transistors in a power integrated circuit technology is presented. Acomprehensive experimental characterization of the important LDMOS electrical parameters over the temperature range 30-300°C is reported. Simple, analytic models are used to explain the observed behavior and to offer physical insight into the effects of temperature on LDMOS performance. A novel test structure is utilized to unambiguously separate channel-region effects from drift-region effects. Using this structure it is shown that the LDMOS channel mobility follows a T -2.5 temperature dependence, which is significantly more severe than the T -1.5 dependence of conventional CMOS channel mobility. Other key temperature- dependent parameters include the threshold voltage, on-state resistance, saturation current, breakdown voltage, and leakage current, which is shown to place a fundamental limitation on the high-temperature operation of the LDMOS transistor.