A new Tree-based coarse-grained FPGA architecture

In this paper, we present a new multilevel hierarchical (tree-based) coarse-grained FPGA architecture. This architecture comprises two unidirectional interconnects, a downward interconnect and an upward interconnect. The proposed architecture can support various kinds of coarse-grained blocks. These coarse-grained blocks are defined using an architecture description file. A new software flow has been developed to evaluate the proposed architecture. New tools are developed to support this software flow and they have resulted in the successful placement and routing of different DSP benchmarks on the proposed architecture. A comparison of coarse-grained tree-based and fine-grained tree-based architectures is performed. This comparison reveals an average area gain of 41% for coarse-grained tree-based architecture over fine-grained tree-based architecture. Similarly a comparison of tree-based and mesh-based coarse-grained architectures shows an average area saving of 60% for tree-based coarse-grained architectures over mesh-based coarse-grained architectures.