An FPGA-Based Neural Network Digital Channel Equalizer

The hardware design of an SCFNN equalizer is presented in this paper. The system is implemented using Verilog hardware description language and has been verified with ALTERA Quartus II. The original equations in the algorithms have been partly rewritten to simplify the hardware design. It has been observed that several multiplications sharing the common operands are performed serially. By using multiplexers and de-multiplexers to replace the multipliers, we have successfully achieved about 30% savings on the hardware cost.