High-level multistep inverter optimization using a minimum number of power transistors

Multilevel inverters with a large number of steps (more than 50 levels) can generate high quality voltage waveforms, good enough to be considered as suitable voltage template generators. Many levels or steps can follow a voltage reference with accuracy, and with the advantage that the generated voltage can be modulated in amplitude instead of pulse-width modulation. The main disadvantage of this type of topology is the large number of power supplies and semiconductors required to obtain these multistep voltage waveforms. This paper is focussed on minimizing the number of power supplies and semiconductors for a given number of levels. Different combinations of topologies are presented, and the corresponding mathematical relations have been derived. This paper shows optimized curves to obtain the relation between a minimum number of power semiconductors required for a given number of levels. Experimental results obtained from an optimized prototype, capable of generatng 81 levels of voltage with only four power supplies and 16 transistors per phase, are shown.