A finite field inversion circuit for high-speed communications

To design a finite field inversion circuit for high-speed communications, we study two variations - that is, square-first and multiply-first type operations - for the repetition-operation of the numerical formula, AB/sub 2/. From these two variations, we propose m-bit parallel semi-systolic architectures for GF(2/sup m/) inversion. When we compared performance of them with those of different inversion architectures based on a normal power-sum operation, based on small grain of special power-sum operation, and based on a Euclidean algorithm, performance of the proposed one, which is based on small grain of special power-sum operation, is the best for the purpose of high-speed applications. When we implement a simplified 8-bit parallel semi-systolic architecture for square-first inversion circuit over GF(2/sup m/) by using 0.25 /spl mu/m CMOS library, it has 2495 equivalent logic-gates, 1848 1-bit latches, and the latency is 56 and the clock-rate is up to 580 MHz at 100% throughput.