A dynamically reconfigurable SIMD processor for a vision chip

Conventional SIMD image processors are very effective for early visual processing because of their parallelism. However, in performing more advanced processing, they exhibit some problems, such as poor performance in global operations and a tradeoff between flexibility of processing and the number of pixels. This paper shows a new architecture and sample algorithms of a vision chip that has the ability to reconfigure its hardware dynamically by chaining processing elements. A prototype chip with 64/spl times/64 pixels manufactured using the 0.35-/spl mu/m CMOS process is also shown.