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Power-efficient trace caches

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4 Author(s)
J. S. Hu ; Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA ; N. Vijaykrishnan ; A. Kandemir ; A. J. Irwin

Summary form only given. This paper exploits the drawbacks of wasting power when accessing the instruction cache that stores only static sequence of instructions. Although trace cache is first introduced to catch the dynamic characteristics of instructions in execution, conventional trace cache (CTC) does increase the power consumption in fetch unit. A Sequential Trace Cache (STC) has been investigated for its power efficiency in this paper

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Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

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