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Mappability estimation of architecture and algorithm

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3 Author(s)
J. -P. Soininen ; VTT Electron., Oulu, Finland ; J. Kreku ; Yang Qu

Method for the selection of processor core and algorithm combinations for system on chip designs is presented. The method uses a mappability concept that is an addition to performance and cost metrics used in codesign. The mappability estimation is based on the analysis of the correlations of algorithm and core characteristics. The method is demonstrated with an analysis tool and the experimental results with DSP cores and algorithms are similar to expectations

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Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

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