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Simple and efficient approach for shunt admittance parameters calculations of VLSI on-chip interconnects on semiconducting substrate

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6 Author(s)
H. Ymeri ; ESAT, Katholieke Univ., Leuven, Heverlee, Belgium ; B. Nauwelaers ; K. Maex ; D. De Roest
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The purpose of this paper is a slight modification of a series expansion method proposed elsewhere for the electrical modeling of lossy-coupled multilayer interconnection lines, that does not involve iterations and yields solutions of sufficient accuracy for most practical interconnections as used in common VLSI chips. We use a Fourier series restricted to cosine functions. The solution for the layered medium is found by matching the potential expressions in the different homogeneous layers with the help of boundary conditions. In the plane of conductors, the boundary conditions are satisfied only at a finite, discrete set of points (point matching procedure)

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Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

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