Substrate noise analysis with compact digital noise injection and substrate models

This paper presents a substrate noise analysis methodology that employs chip-level substrate modeling based on F-matrix computation and digital substrate-noise injection modeling with a time-series divided parasitic capacitance model for time-domain power-supply current estimation. System-level simulation models generated according to the methodology provide reliable substrate noise waveforms. Simulated waveforms for practical digital circuits on a 0.6-μm CMOS 4.5-mm square chip are consistent with measurements with 100-ps 100-μV resolution. Peak-to-peak substrate noise amplitudes for reduced-substrate noise as well as conventional designs show roughly an error of 10% compared with the measurements