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Ultrathin NH3 annealed atomic layer deposited Si-nitride/SiO2 stack gate dielectrics with high reliability

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4 Author(s)
Q. D. M. Khosru ; Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan ; A. Nakajima ; T. Yoshimoto ; S. Yokoyama

MOS capacitors are fabricated with ultrathin (equivalent oxide thickness, EOT=2.1 nm) atomic layer deposited (ALD) Si-nitride/SiO2 stack gate dielectrics annealed in NH3 at a moderate temperature of 550°C. Excellent performances in the reduction of leakage currents and electrical stress induced degradations are exhibited by these capacitors. An interesting feature of suppressed soft breakdown events is observed in ramped voltage stressing experiments and constant electric field induced time-dependent dielectric breakdown measurements. The capacitors also exhibited excellent interface quality, lower bulk trap density, lower trap generation rate and higher reliability in comparison with the capacitors fabricated with conventional thermal SiO2 dielectrics as well as with ALD Si-nitride/SiO2 stack dielectrics without NH3 annealing. The proposed stack gate dielectric appears to be very promising for ULSI devices.

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Semiconductor Device Research Symposium, 2001 International

Date of Conference: