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Development of CVD-Ru/Ta/sub 2/O/sub 5//CVD-Ru capacitor with concave structure for multigigabit-scale DRAM generation

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9 Author(s)
Wan-Don Kim ; Semicond. R&D Center, Samsung Electron. Co., Ltd, Kyungki-Do, South Korea ; Jae-Hyun Joo ; Yong-Kuk Jeong ; Seok-Jun Won
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RIR(Ru/Crystalline-Ta/sub 2/O/sub 5/Ru) capacitor with concave structure was studied for the application into multigigabit-scale DRAM device. In this work, several novel technologies were successfully developed to solve current issues in the fabrication of RIR concave capacitor; such as 1) two-step deposition of Ta/sub 2/O/sub 5/ films 2) formation of Ta/sub 2/O/sub 5/ spacer 3) new separation process of Ru storage node using maskless etch-back method 4) H/sub 2/ pre-annealing and 5) Ar plasma pre-treatment on Ru bottom electrode. The RIR concave capacitor (design rule/spl sim/0.12 /spl mu/m, node height/spl sim/0.85 /spl mu/m) fabricated with these novel technologies showed excellent electrical properties (25fF/cell, 1fA/cell at /spl plusmn/ 1V), which indicates that RIR structure is the one of the most promising candidate for the next generation DRAM capacitor.

Published in:

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Date of Conference:

2-5 Dec. 2001