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A 50-nm CMOS technology for high-speed, low-power, and RF applications in 100-nm node SoC platform

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9 Author(s)
Ohnishi, K. ; Central Res. Lab., Hitachi Ltd., Kokubunji, Japan ; Tsuchiya, R. ; Yamauchi, T. ; Ootsuka, F.
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We have developed 100-nm node CMOS platform mixed with high performance and low-power/RF applications. This platform is featured by an Offset Source/Drain structure for gate length reduction without reducing drive current, and by a SSC (Super Steep Channel) profile for improving low-power/RF performance in terms of carrier mobility and 1/f noise.

Published in:

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Date of Conference:

2-5 Dec. 2001