By Topic

The ballistic FET: design, capacitance and speed limit

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Solomon, P.M. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Laux, S.E.

In this paper we present a design methodology for the ballistic FET (BFET) which illuminates many topics currently under discussion such as the injection velocity, the role of the contacts, and the meaning of the capacitance and mobility. Both InGaAs/InAlAs in the 20-30 nm gate length range, and Si/SiO/sub 2/ FETs in the 10-20 nm range are simulated using Monte Carlo techniques, where the InGaAs FETs are almost purely ballistic, whereas the Si FETs were not. Expressions for the BFET drain current are derived in the extreme quantum limit and for zero thickness gate insulator, where the importance of the degeneracy capacitance is emphasized. An ultimate speed limit for the BFET is derived.

Published in:

Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International

Date of Conference:

2-5 Dec. 2001