Narrow distribution of threshold voltages in 4 Mbit MONOS memory-cell arrays and its impact on cell operation

This paper describes the narrow and non-spread distribution of threshold voltage in MONOS (Metal-oxide-nitride-oxide-semiconductor) memory cell array. We fabricated 4 Mbit MONOS memory test chip using 0.25 /spl mu/m technology. The gate length of the memory cell is shrunk to 0.18 /spl mu/m. The distributions of threshold voltage in many operations are evaluated. As a result range of the distribution of threshold voltage keeps narrow in program and erase operation. It also keeps narrow in heat treatment of 300/spl deg/C. These characteristics are also good advantages of MONOS memory device for multi-bit memory applications. It is also shown that there is a possibility to achieve non-verify operation in both program and erase cycle. The MONOS memory device is a promising form of nonvolatile memory for use in cheaper than floating gate (FG) yet highly reliable embedded applications.