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Analytical thermal model for multilevel VLSI interconnects incorporating via effect

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3 Author(s)
Ting-Yen Chiang ; Center for Integrated Syst., Stanford Univ., CA, USA ; Banerjee, K. ; Saraswat, K.C.

The authors present compact analytical thermal models for estimating the temperature rise of multilevel VLSI interconnect lines incorporating via effect. The impact of vias has been modeled using (1) a characteristic thermal length and (2) an effective thermal conductivity of ILD (interlayer dielectric), k/sub ILD,eff/, with k/sub ILD/,/sub eff/=k/sub ILD//spl eta//, where /spl eta/ is a physical correction factor, with 0

Published in:

Electron Device Letters, IEEE  (Volume:23 ,  Issue: 1 )

Date of Publication:

Jan. 2002

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