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Evaluating the impact of architectural-level optimizations on clock power

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4 Author(s)
D. Duarte ; Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA ; V. Narayanan ; M. J. Irwin ; M. Kandemir

A clock energy model is incorporated into a cycle-accurate energy simulator for an embedded architecture, which also resembles processor cores present in System-on-a-Chip (SoC) designs. This framework is used to study and quantify the influence on clock energy of several architectural-level decisions and their relative impact on the overall system energy. The design cases include various cache architectures and support for clock gating at different levels (global and local). At the software level, the influence on clock energy of power-oriented memory compiler optimizations is assessed

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ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference: