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A true block pipelined programmable Reed-Solomon CODEC for high-speed/low-power applications

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4 Author(s)
Hyung-Joon Kwon ; Samsung Electron., Kyunggi-Do, South Korea ; Jaeshin Lee ; Seunghoon Lee ; Bong Young Jeong

Proposes a Reed-Solomon CODEC architecture. The chip was fabricated using 0.35μm technology. Since it was implemented as a programmable CODEC which,can correct up to 16 errors/32 erasures at once, it has versatility regardless of the number of correctable errors and the length of codeword for various applications. Suggested RS-CODEC has "true block pipelined architecture" in which frame latency is equal to the length of codeword leading to maximize throughput to achieve high-speed and low-power at the same time. The input data rate can amount to 100MByte per sec

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference:

2001