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SCALIP - a scalable IP solution for pipelined arrays with limited feedback

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2 Author(s)
Moe, M. ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA ; Schmit, H.

Current IP methodologies are only useful within a limited design space low power, high performance or low area. A single IP methodology is needed that can span all of these design spaces with one specification. SCALIP is a methodology that can quickly and easily create multiple design points that span a much greater design space thin any current IP methodology utilizing only behavioral or RTL synthesis. One limitation of this methodology is that it is only useful for pipelined arrays with limited feedback

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference:

2001