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Reuse of addressable system bus for SOC testing

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2 Author(s)
Sungbae Hwang ; Comput. Eng. Res. Center, Texas Univ., Austin, TX, USA ; Abraham, J.A.

Describes a novel test methodology for core-based SOCs. The methodology is based on the use of the existing system bus and/or peripheral bus to access the ports on embedded cores. The microprocessor situated in an SOC can access the addressable terminals of embedded cores to feed test stimuli and to read captured test responses. This novel approach does not need additional bus structures from chip I/Os to cores for the test access mechanism; hence it significantly reduces area overhead and enables the use of the microprocessor's computing power to control the test process of the deeply embedded cores on an SOC

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ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

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