By Topic

Reprogrammable processing capabilities of embedded FPGA blocks

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
T. Vaida ; LSI Logic Corp., Boulder, CO, USA

Modern signal processing applications and other compute intensive algorithms can be implemented in fixed ASIC logic to improve performance. The drawback of doing so is that the design is forever fixed with a standard, protocol or algorithm. The availability of embeddable FPGA cells in ASIC systems allows the designer to set the algorithm in 'reprogrammable' logic. Further, the embedded LiquidLogic core (LL) architecture from LSI Logic, provides the ability to manipulate the implemented algorithm at run-time allowing the design to adapt the function in real-time. This paper presents a theoretical ASIC design that utilizes these capabilities and describes dependencies for developing a class of SoC devices

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference: