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Cell designs for self-timed FPGAs

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3 Author(s)
Traver, C. ; Dept. of Electr. Eng. & Comput. Sci., Union Coll., Schenectady, NY, USA ; Reese, R.B. ; Thornton, M.A.

A self-timed programmable architecture used for the implementation of Phased Logic (PL) systems is described. PL systems are automatically translated from clocked designs and result in self-timed circuits that are insensitive to delays between gates. The target implementation is a self-timed FPGA architecture composed of PL gates. A PL gate design based on a 4-input lookup table is presented. Power and performance estimates of two designs are given and are compared to their clocked counterparts

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference:

2001