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A novel all digital phase locked loop (ADPLL) with ultra fast locked time and high oscillation frequency

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2 Author(s)
Kuo-Hsing Cheng ; Dept. of Electr. Eng., Tarnkam Univ., Taipei, Taiwan ; Yu-Jung Chen

In this paper a new architecture for all digital phase locked loop (ADPLL) is proposed The new architecture is based on the ADPLL architecture proposed by Motorola in 1995 but modified in some block A new binary search decision scheme was used to accelerate the frequency acquisition process. It can reduce the chip area and increase the operating frequency. In this design, a 14-bit control word is used to control the digital control oscillator. The new type ADPLL has been designed and implemented by TSMC's 0-35 μ IP4M CMOS process for 3.3V applications. The phase lock process takes 20-reference cycle, and the maximum frequency of the proposed ADPLL is about 820MHz

Published in:

ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

Date of Conference:

2001