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Integrated approach to optimized code generation for heterogeneous-register architectures with multiple data-memory banks

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2 Author(s)
S. Frohlich ; Inst. of Commun. & Radio-Frequency Eng., Vienna Univ. of Technol., Austria ; B. Wess

This paper focuses on heterogeneous-register architectures with multiple data-memory banks. An evolutionary hybrid is introduced that combines evolutionary optimization strategies with tree techniques and list scheduling. It minimizes the execution time of the final code by jointly optimizing the schedule, selected instructions, allocated registers and data memory banks. The core of the proposed technique is a linear-time algorithm translating expression trees into optimal straight-line code segments. Topically, the proposed technique executes an order of magnitude faster than pure genetic implementations and achieves better results than with successively applied greedy techniques for the individual code generation steps. The proposed technique is well-suited to applications with stringent timing constraints

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ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

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