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Demonstration of power enhancements on an industrial circuit through delay management of non-critical data paths

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6 Author(s)
Velenis, D. ; Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA ; Tang, T.K. ; Kourtev, I.S. ; Adler, V.
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On-chip power dissipation has become a fundamental design issue in high performance integrated circuits. A technique to significantly reduce the power dissipated in the non-critical data paths of an industrial circuit is demonstrated. The application of this technique with non-zero clock skew scheduling to the slower data paths is also described. Simulation results demonstrating the application of this technique to certain functional blocks of a high performance microprocessor are presented. A greater than 80% power savings is achieved in specific circuit blocks

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ASIC/SOC Conference, 2001. Proceedings. 14th Annual IEEE International

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