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On effective I/sub DDQ/ testing of low-voltage CMOS circuits using leakage control techniques

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3 Author(s)
Zhanping Chen ; Intel Corp., Hillsboro, OR, USA ; Liqiong Wei ; K. Roy

The use of low-threshold devices in low-voltage CMOS circuits leads to an exponential increase in the intrinsic leakage current. This threatens the effectiveness of I/sub DDQ/ testing for such low-voltage circuits because it is difficult to differentiate a defect-free circuit from defective circuits. Recently, several leakage control techniques have been proposed to reduce intrinsic leakage current, which may benefit I/sub DDQ/ testing. In this paper, we investigate the possibilities of applying different leakage control techniques to improve the fault coverage of I/sub DDQ/ testing. Results on a large number of benchmarks indicate that dual-threshold and vector control techniques can be very effective in improving fault coverage for I/sub DDQ/ testing for some circuits.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:9 ,  Issue: 5 )