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Multiclock selection and synthesis for CDFGs using optimal clock sets and genetic algorithms

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2 Author(s)
Torbey, E. ; Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada ; Knight, J.P.

Selecting a clock period is an essential step in implementing hardware from behavioral descriptions. Current methods either estimate the clock prior to scheduling or involve exhaustive runs of the high-level synthesis tools to obtain a globally optimum clock period. Further, the potential benefits of allowing the use of multiple clocks for performance optimization has not been investigated. This paper presents a clock selection method that works simultaneously with synthesis by selecting a clock from an optimal clock set. The synthesis is iterative and is optimized by evolutionary techniques. The method is very flexible and can accommodate a large set of potentially optimal clocks. We also present multirate clock synthesis with path-dependent clock selection where different paths in a control data flow graph (CDFG) are optimized with different clock periods. The results shown prove the method's effectiveness.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:9 ,  Issue: 5 )