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High speed dynamic fault-tolerance

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2 Author(s)
J. Sengupta ; Dept. of Comput. Sci. & Eng., Punjabi Univ., Patiala, India ; P. Bansal

Multistage interconnection networks have been used as a favored ATM switch fabric. This paper analyzes the fault-tolerance and performance abilities of the proposed Phi network and compares it with its predecessor, the Omega network. The reduced numbers of stages of the designed MIN diminish the latency within the network markedly. The methods for routing permutations in the presence and absence of faulty components in both the networks have been analytically compared. The irregular nature of the Phi network allows 50% of the permutations to pass at the minimum path length of 2 whereas others pass at adaptable path length counting on the status of the path, largest being log2 N for a network of size N. The bandwidth of the new network shows optimal benefits. Bounds on reliability exhibit graceful degradation with time showing distinct gains over Omega where it reduces drastically, increasing the time between failures of the system. The comparison of these networks shows that irregular Phi network is a preferred choice to be used in the high-speed multiprocessor environment

Published in:

TENCON 2001. Proceedings of IEEE Region 10 International Conference on Electrical and Electronic Technology  (Volume:2 )

Date of Conference:

2001