By Topic

A low power register scheduling and allocation algorithm for multiple voltage

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Choi, J.-Y. ; Dept. of Electron. Eng., Chongju Univ., China ; Chi-Ho Lin ; Hi-Seok Kim

The low power register scheduling and allocation algorithm is concerned with minimum switching activity and low power multiple voltages. The proposed algorithm executes low power scheduling to reduce switching activity using a shut down technique by the creation of a data flow graph (DFG) from the VHDL description. Also, the low power register allocation algorithm determines the minimum register after the life time analysis of all variables. It minimizes the switching activity using a graph coloring technique for low power consumption. Finally, the total power is reduced by using the low power multiple voltage. The proposed algorithm proves the effect through various filter benchmarks to adopt a low power register scheduling and allocation algorithm considering resource constraint at multiple voltage

Published in:

TENCON 2001. Proceedings of IEEE Region 10 International Conference on Electrical and Electronic Technology  (Volume:2 )

Date of Conference:

2001