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Fault characterizations and design-for-testability technique for detecting IDDQ faults in CMOS/BiCMOS circuits

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2 Author(s)
K. Raahemifar ; Electr. & Comput. Eng. Dept., Ryerson Polytech. Inst., Toronto, Ont., Canada ; M. Ahmadi

This paper provides the results of a simulation-based fault characterization study of CMOS/BiCMOS logic families. We show that most of the shorts cause lDDQ faults, while open defects result in delay or stuck-open faults. We propose a design-for-testability technique for detecting short and bridging faults in CMOS/BiCMOS logic circuits. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated.

Published in:

Design Automation Conference, 2001. Proceedings

Date of Conference:

2001