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Combining low-power scan testing and test data compression for system-on-a-chip

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2 Author(s)
A. Chandra ; Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA ; K. Chakrabarty

We present a novel technique to reduce both test data volume and scan power dissipation using test data compression for system-on-a-chip testing. Power dissipation during test mode using ATPG-compacted test patterns is much higher than during functional mode. We show that Golomb coding of precomputed test sets leads to significant savings in peak and average power, without requiring either a slower scan clock or blocking logic in the scan cells. We also improve upon prior work on Golomb coding by showing that a separate cyclical scan register is not necessary for pattern decompression. Experimental results for the larger ISCAS 89 benchmarks show that reduced test data volume and low power scan testing can indeed be achieved in all cases.

Published in:

Design Automation Conference, 2001. Proceedings

Date of Conference:

22-22 June 2001