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Instruction-level DfT for testing processor and IP cores in system-on-a-chip

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2 Author(s)
Wei-Cheng Lai ; Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA ; Kwang-Ting Cheng

Self-testing manufacturing defects in a system-on-a-chip (SOC) by running test programs using a programmable core has several potential benefits including, at-speed testing, low DfT overhead due to elimination of dedicated test circuitry and better power and thermal management during testing, However, such a self-test strategy might require a lengthy test program and might not achieve a high enough fault coverage. We propose a DfT methodology to improve the fault coverage and reduce the test program length, by adding test instructions to an on-chip programmable core such as a microprocessor core. This paper discusses a method of identifying effective test instructions which could result in highest benefits with low area/performance overhead. The experimental results show that with the added test instructions, a complete fault coverage for testable path delay faults can be achieved with a greater than 20% reduction in the program size and the program runtime, as compared to the case without instruction-level DfT.

Published in:

Design Automation Conference, 2001. Proceedings

Date of Conference:

2001

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