Design considerations for ISO/IEC 13818-1 decoders

Important design considerations, principles and tradeoffs applied to the design of MPEG-2 transport stream demultiplexers suitable for integration with MPEG video/audio decoders and 2D/3D graphics core are presented. The described architecture integrates demultiplexing of the most frequent transport packets of MPEG HDTV video and audio streams into the register based hardware core and all digital teletext/subtitling decoding functions and user or private data processing on low to midrange performance host CPU (Pentium 200 MHz or MIPS 166 MHz). This results in the greater flexibility and reduction of the hardware cost of digital set-top receivers.