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Single chip video processor for digital HDTV

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5 Author(s)
H. Yamauchi ; Sanyo Electr. Co. Ltd., Gifu, Japan ; S. Okada ; K. Taketa ; Y. Mihara
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We have developed a new high-performance video system LSI using a 0.25 μm CMOS technology for Japan BS digital broadcasting launched in December 2000. The LSI integrates all the necessary functions for video decoding into a single chip and employs efficient architectures which are parallel processing and have parallel data bus architecture for decoding transport streams efficiently

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Consumer Electronics, 2001. ICCE. International Conference on

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