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Fully integrated 2.2 mW CMOS front-end for a 900 MHz zero-IF wireless receiver

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2 Author(s)
S. Mahdavi ; Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA ; A. A. Abidi

Wireless sensors and wearable wireless devices need low bit-rate receivers which dissipate a total power of less than 5 mW and operate from a single cell. They must also be highly integrated for small physical volume. As is customary, CMOS is the technology of choice. In previous work, we have developed a complete 900 MHz receiver for FLEX paging signals which dissipates 4.5 mW from 1.5V, but needs several high quality off-chip inductors. This work advances the state of the art by integrating these external components in the RF and IF sections of a 900 MHz zero-IF receiver. There are three design challenges: (a) Low current consumption, (b) low voltage operation, and (c) low 1/f noise at zero IF. Integrated in 0.35/spl mu/m CMOS, the receiver front-end including LNA and two mixer stages dissipates only 2.2 mW. As low power design is a universal concern in RF-IC design, the methodology described here is expected to be of value in many other applications.

Published in:

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

14-16 June 2001