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A reconfigurable multilevel parallel graphics cache memory with 75 GB/s parallel cache replacement bandwidth

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8 Author(s)
Se-Jeong Park ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea ; Jeong-Su Kim ; Ramchan Woo ; Se-Joong Lee
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A dedicated single-chip multilevel parallel graphics cache memory for high-speed parallel texture mapping in PC graphics has been fabricated by a 0.16 /spl mu/m DRAM technology. The proposed cache architecture is composed of four components: 1) an 8 MB DRAM L2 cache, 2) eight 16 KB SRAM L1 parallel caches, 3) eight pipelined texture data filters, 4) serial-to-parallel latches. The refill bandwidth of the parallel L1 cache is maximized up to 75 GB/sec by a hidden double data transfer scheme between the L2 and L1 caches. Furthermore, by adaptive sub-wordline activation scheme, the line sizes of the L2 and L1 caches are reconfigurable for achieving optimal cache miss rate and lower power consumption. The SRAM L1 caches and the texture filters by use of parallel pipelined structures result in higher system performance.

Published in:

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

14-16 June 2001