A 800 MHz single cycle access 32 entry fully associative TLB with a 240 ps access match circuit

A high-speed content addressable memory (CAM) match circuit is the key for a system LSI in this digital network era, such as consumer electronics and digital communication. For example, a microprocessor with a memory management unit (MMU) has usually a translation look-aside buffer (TLB) including the CAM. The CAM is demanded small area, high speed, and also low power. In this paper we propose and study two types of CAM match circuit for a fully associative TLB.