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7th order equiripple filter with cutoff frequency of 200 MHz is developed in a 0.25 /spl mu/m CMOS process. A new design method has been adopted to obtain enough accuracy and linearity in high frequency operation. Optimal device sizes are determined that maximize the accuracy. The most suitable filter configuration is determined that suppresses the nonlinearity of the transconductors. Experimental results satisfy group delay variation of /spl plusmn/5% and THD of less than 1% for a 400 mVpp differential input.