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A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM

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7 Author(s)
Miwa, T. ; Silicon Syst. Res. Lab., NEC Corp., Sagamihara, Japan ; Yamada, J. ; Koike, H. ; Nakura, T.
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This paper describes two new circuit techniques for nonvolatile SRAMs with back-up ferroelectric capacitors (NV-SRAMs). These circuits are able to overcome the size and low-voltage-reliability problems faced by the original NV-SRAM. A new 0.25-/spl mu/m-design-rule four-metal-layer NV-SRAM cell occupies 9.7 /spl mu/m/sup 2/, that is the same area as a 0.25-/spl mu/m three-metal-layer SRAM cell. A high-voltage/negative-voltage plate line driver allows a low-voltage-operation NV-SRAM array to improve its nonvolatile retention characteristics. A 512 Kbit test macro has also been designed with only one percent area overhead from a conventional SRAM macro.

Published in:
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference: 14-16 June 2001

Page(s):
129 - 132
Meeting Date :
14 Jun 2001-16 Jun 2001
Print ISBN:
4-89114-014-3
INSPEC Accession Number:
7081204
Conference Location :
Kyoto, Japan
Digital Object Identifier :
10.1109/VLSIC.2001.934217
Product Type:
Conference Publications

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