Referenced Items are not available for this document.
We propose a sense scheme in which a pMOS charge-transfer maintains the bit-line level near the GND level when the plate line goes high. The scheme supplies 0.5 V higher read-out voltages across the cell capacitors and achieves a 0.4 V higher differential amplitude in a 512-cell per bit-line structure than a conventional DRAM sense scheme. A shifted bias plate line layout enables a minimum number of bit-lines to be activated and achieves 8.06 mW at 3 V, 5 MHz, about same power as a conventional device.
Published in:
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Date of Conference: 14-16 June 2001
- Page(s):
- 127 - 128
- Meeting Date :
- 14 Jun 2001-16 Jun 2001
- Print ISBN:
- 4-89114-014-3
- INSPEC Accession Number:
- 7081203
- Conference Location :
- Kyoto, Japan
- Digital Object Identifier :
- 10.1109/VLSIC.2001.934216
- Product Type:
- Conference Publications
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