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Automatic calibration of modulated /spl Sigma/-/spl Delta/ frequency synthesizers

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2 Author(s)
McMahill, D.R. ; MIT, Cambridge, MA, USA ; Sodini, C.G.

This paper describes a sigma-delta (/spl Sigma/-/spl Delta/) synthesizer for Gaussian frequency and minimum shift keying (GFSK/GMSK) modulation. The key innovation is an in-service automatic calibration circuit which tunes the phase locked loop (PLL) to compensate for process tolerance and temperature variation. The PLL, including 1.8 GHz voltage controlled oscillator (VCO), /spl Sigma/-/spl Delta/ modulator, and calibration circuit has been implemented in a 0.6 micron BiCMOS integrated circuit. The test chip achieves 2.5 Mbit/second using GFSK and 5.0 Mbit/second using 4-FSK.

Published in:

VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on

Date of Conference:

14-16 June 2001

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