Referenced Items are not available for this document.
This paper presents the design of a fully-integrated CMOS frequency synthesizer for PCS- and cellular-CDMA wireless systems. The proposed charge-averaging charge pump scheme suppresses fractional spurs and the VCO combined with coarse tuning improves phase noise characteristics. The improved architecture of the dual-path loop filter makes it possible to implement a large time constant on a chip. Fabricated in 0.35-/spl mu/m CMOS technology, this circuit provides 10 kHz channel spacing with phase noise of -106 dBc/Hz at 100 kHz offset. Power dissipation is 60 mW with 3.0 V supply.
Published in:
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Date of Conference: 14-16 June 2001
- Page(s):
- 43 - 46
- Meeting Date :
- 14 Jun 2001-16 Jun 2001
- Print ISBN:
- 4-89114-014-3
- INSPEC Accession Number:
- 7092015
- Conference Location :
- Kyoto, Japan
- Digital Object Identifier :
- 10.1109/VLSIC.2001.934190
- Product Type:
- Conference Publications
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