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A 64-tap CMOS echo canceller/decision feedback equalizer for 2B1Q HDSL transceivers

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5 Author(s)
Samueli, H. ; Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA ; Daneshrad, B. ; Joshi, R.B. ; Wong, B.C.
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A 60-MHz 64-tap adaptive finite-impulse-response (FIR) filter chip was fabricated in 1.2-μm CMOS. It can implement either an echo canceler or a decision feedback equalizer for 2B1Q high bit rate digital subscriber line (HDSL) transceivers. The 4.3×4.3 mm2, 30000 transistor chip is a completely self-contained adaptive filter which incorporates the least mean square (LMS) algorithm for coefficient updating. The device can be cascaded to implement very long filter lengths, which are often required in high bit rate transceivers. At a 60-MHz clock rate, the echo canceler/decision feedback equalizer chip can accommodate symbol rates in excess of 800 kbaud

Published in:

Selected Areas in Communications, IEEE Journal on  (Volume:9 ,  Issue: 6 )

Date of Publication:

Aug 1991

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