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Yield optimization in the mature fab

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3 Author(s)
Effron, M. ; HPL Corp. Inc., San Jose, CA, USA ; Carlson, B. ; Hiscock, D.

This paper provides the authors' insights and discussions in four areas of yield optimization available to the mature semiconductor fabricator. The mature fab is arbitrarily defined as fabs older than 3 years having feature sizes of >0.5 μm. The areas of yield optimization include: (1) cost and implementation considerations for an integrated data collection and information analysis system; (2) use of a quantified and partitioned D0 yield model; (3) focus on baseline yield quantification and improvement practices versus excursion controls; (4) increased roles and responsibilities for yield improvement

Published in:

Advanced Semiconductor Manufacturing Conference, 2001 IEEE/SEMI

Date of Conference:

2001