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A digital common-mode rejection technique for differential analog-to-digital conversion

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2 Author(s)
E. Fogleman ; Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA ; I. Galton

A multibit ΔΣ analog-to-digital converter can achieve high resolution with a lower order ΔΣ modulator and lower oversampling ratio than a single-bit design, but it requires a multibit internal flash analog-to-digital converter rather than a simple comparator. In an implementation with a fully differential analog front end, the flash analog-to-digital converter must quantize a differential voltage relative to a set of differential reference voltages. Though analog techniques for differential analog-to-digital conversion exist, implementing them in a low-voltage single-poly CMOS process is a challenging circuit design problem. This paper presents a digital common-mode rejection technique for differential analog-to-digital conversion (ADC), which avoids the circuit complexity and die area requirements of analog common-mode rejection techniques. This technique was used to implement the internal quantizer in two high-performance single-poly CMOS ADC ΔΣ modulator prototypes with over 98-dB peak signal-to-noise-and-distortion ratio and 105-dB spurious-free dynamic range. Implementation details, die area requirements, and measured common-mode rejection are presented for the prototype. Signal-processing details of digital common-mode rejection within the ΔΣ modulator are presented, showing that injected common-mode noise results only in modulation of the quantization error power and does not create spurious tones

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IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:48 ,  Issue: 3 )