Cycle-true leakage current modeling for CMOS gates

This paper addresses cycle-true leakage current modeling for static CMOS gates. An approach to leakage power estimation is suggested which deals with some of the issues associated with the complex dynamic behavior of the gate. The paper discusses problems with defining gate leakage power. It then suggests a modeling approach, which separates the static leakage from the dynamic switch and short-circuit power. The model is used to achieve cycle-true leakage power estimation which is important as 20% of the power consumption in the designs of today can be leakage power. The importance of leakage power modeling will continue to grow as leakage power scales exponentially with reduced V/sub T/.