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Gate-level simulation of CMOS circuits using the IDDM model

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5 Author(s)
M. J. Bellido ; Inst. de Microelectron. de Sevilla, Sevilla, Spain ; J. Juan-Chico ; P. Ruiz de Clavijo ; A. J. Acosta
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Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is able to take account of the propagation of arbitrarily narrow pulses. As a result, the model is ready to be applied to the simulation and verification of complex circuits. Simulation results show an accuracy similar to HSPICE and greatly improved precision over conventional delay models

Published in:

Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

Date of Conference: