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A pattern compaction technique for power estimation based on power sensitivity information

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3 Author(s)
Chih-Yang Hsu ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Chaur-Wen Wei ; Wen-Zen Shen

We propose an efficient power estimation technique for CMOS combinational circuits based on power sensitivity information of primary inputs. We compacted a large sequence of input patterns into a much smaller ones, which also preserved the statistical properties of the original sequence. The experimental results showed our compaction method achieved high compaction ratio within reasonable loss in the accuracy for average power estimation

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Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

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