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Energy efficient signaling in DSM CMOS technology

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4 Author(s)
Dhaou, I.B. ; Electron. Syst. Design Lab., R. Inst. of Technol., Kista, Sweden ; Tenhunen, H. ; Sundararajan, V. ; Parhi, K.K.

The problem of efficient signaling over on-chip interconnect in DSM technology is addressed. A signaling scheme based on low-swing combined with repeater insertion and resizing is derived for both cascaded inverters and inverter chains. The proposed scheme has been implemented in 0.25 μm 2.5 V, 6 metal layers CMOS process. HSPICE results showed that our scheme leads to a substantial energy-saving ratio without speed degradation

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Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on  (Volume:5 )

Date of Conference: